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MM74C240 * MM74C244 Inverting * Non-Inverting Octal Buffer and Line Driver with 3-STATE Outputs
October 1987 Revised May 2002
MM74C240 * MM74C244 Inverting * Non-Inverting Octal Buffer and Line Driver with 3-STATE Outputs
General Description
The MM74C240 and MM74C244 octal buffers and line drivers are monolithic complementary MOS (CMOS) integrated circuits with 3-STATE outputs. These outputs have been specially designed to drive highly capacitive loads such as bus-oriented systems. These devices have a fan out of 6 low power Schottky loads. A high logic level on the output disable control input G makes the outputs go into the high impedance state.
Features
s Wide supply voltage range (3V to 15V) s High noise immunity (0.45 VCC typ) s Low power consumption s High capacitive load drive capability s 3-STATE outputs s Input protection s TTL compatibility s 20-pin dual-in-line package s High speed 25 ns (typ.) @ 10V, 50 pF (MM74C244)
Ordering Code:
Order Number MM74C240WM MM74C240N MM74C244WM MM74C244N Package Number M20B N20A M20B N20A Package Description 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide 20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide 20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide 20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide
Devices also available in Tape and Reel. Specify by appending suffix letter "X" to the ordering code.
Connection Diagrams
MM74C240 MM74C244
(Top View)
(Top View)
(c) 2002 Fairchild Semiconductor Corporation
DS005905
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MM74C240 * MM74C244
Logic Diagrams
MM74C240 MM74C244
Truth Tables
MM74C240 ODA 1 1 0 0 ODB 1 1 0 0
1 = HIGH 0 = LOW
MM74C244 OA Z Z 1 0 OB Z Z 1 0
X = Don't Care Z = 3-STATE
IA X X 0 1 IB X X 0 1
ODA 1 1 0 0 ODB 1 1 0 0
IA X X 0 1 IB X X 0 1
OA Z Z 0 1 OB Z Z 0 1
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MM74C240 * MM74C244
Absolute Maximum Ratings(Note 1)
Voltage at Any Pin Operating Temperature Range Storage Temperature Range Power Dissipation Dual-In-Line Small Outline Operating VCC Range Absolute Maximum VCC Lead Temperature (Soldering, 10 seconds) 260C 700 mW 500 mW 3V to 15V 18V
Note 1: "Absolute Maximum Ratings" are those values beyond which the safety of the device cannot be guaranteed. Except for "Operating Range" they are not meant to imply that the devices should be operated at these limits. The Electrical Characteristics table provides conditions for actual device operation.
-0.3V to VCC + 0.3V -55C to +125C -65C to +150C
DC Electrical Characteristics
Min/Max limits apply across temperature range, unless otherwise noted Symbol Parameter Conditions CMOS TO CMOS VIN(1) VIN(0) VOUT(1) VOUT(0) IOZ IIN(1) IIN(0) ICC VIN(1) VIN(0) VOUT(1) VOUT(0) ISOURCE Logical "1" Input Voltage Logical "0" Input Voltage Logical "1" Output Voltage Logical "0" Output Voltage 3-STATE Output Current Logical "1" Input Current Logical "0" Input Current Supply Current Logical "1" Input Voltage Logical "0" Input Voltage Logical "1" Output Voltage Logical "0" Output Voltage Output Source Current (P-Channel) VCC = 5V VCC = 10V VCC = 5V VCC = 10V VCC = 5V, I O = -10 A VCC = 10V, IO = -10 A VCC = 5V, I O = 10 A VCC = 10V, IO = 10 A VCC = 10V, OD = VIH VCC = 15V, VIN = 15V VCC = 15V, VIN = 0V VCC = 15V VCC = 4.75V VCC = 4.75V VCC = 4.75V, IO = -450 A VCC = 4.75V, IO = -2.2 mA VCC = 4.75V, IO = 2.2 mA VCC = 5V, V OUT = 0V TA = 25C VCC = 10V, VOUT = 0V TA = 25C ISINK Output Sink Current (N-Channel) VCC = 5V, V OUT = VCC TA = 25C VCC = 10V, VOUT = VCC TA = 25C 48 70 mA 12 20 mA -36 -70 mA -14 -30 OUTPUT DRIVE (See Family Characteristics Data Sheet) (Short Circuit Current) mA VCC - 0.4 2.4 0.4 VCC - 1.5 0.8 -1.0 0.005 -0.005 0.05 300 4.5 9.0 0.5 1.0 10 1.0 3.5 8.0 1.5 2.0 V V V V A A A A V V V V V Min Typ Max Units
CMOS/LPTTL INTERFACE
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MM74C240 * MM74C244
AC Electrical Characteristics
TA = 25C, CL = 50 pF, unless otherwise specified Symbol tPD(1), tPD(0) Parameter Propagation Delay (Data In to Out) MM74C240
(Note 2)
Conditions Min Typ Max Units
VCC = 5V, CL = 50 pF VCC = 10V, CL = 50 pF V CC = 5V, CL = 150 pF VCC = 10V, CL = 150 pF
60 40 80 60 45 25 60 40 45 35 50 30 45 30 75 50
90 70 110 90 70 50 90 70 80 60 90 60 80 60 140 100 ns ns ns
MM74C244
V CC = 5V, CL = 50 pF VCC = 10V, CL = 50 pF VCC = 5V, CL = 150 pF VCC = 10V, CL = 150 pF
t1H, t0H
Propagation Delay Output Disable to High Impedance State (from a Logic Level)
RL = 1k, CL = 50 pF VCC = 5V VCC = 10V RL = 1k, CL = 50 pF VCC = 5V VCC = 10V VCC = 5V, CL = 50 pF VCC = 10V, CL = 50 pF VCC = 5V, CL = 150 pF VCC = 10V, CL = 150 pF ns ns
tH1, tH0
Propagation Delay Output Disable to Logic Level (from High Impedance State)
tT(HL), tT(LH) Transition Time
CPD
Power Dissipation Capacitance (Output Enabled per Buffer) MM74C240 MM74C244 (Output Disabled per Buffer) MM74C240 MM74C244
(Note 3)
100 100 10 0 VIN = 0V, f = 1 MHz, TA = 25C VIN = 0V, f = 1 MHz, TA = 25C 10 10
pF
pF pF pF
CIN CO
Input Capacitance (Note 4) (Any Input) Output Capacitance (Note 4) (Output Disabled)
Note 2: AC Parameters are guaranteed by DC correlated testing. Note 3: CPD determines the no load AC power consumption of any CMOS device. For complete explanation see Family Characteristics Application Note, AN-90. Note 4: Capacitance is guaranteed by periodic testing.
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MM74C240 * MM74C244
Typical Application
Typical Performance Characteristics
N-Channel Output Drive at 25C P-Channel Output Drive at 25C
MM74C240 Propagation Delay vs. Load Capacitance
MM74C244 Propagation Delay vs. Load Capacitance
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MM74C240 * MM74C244
AC Test Circuits and Switching Time Waveforms
tpd0, tpd1 t1H and tH1
t0H and tH0
Note: Delays measured with input tr, tf 20 ns.
CMOS to CMOS
t1H and tH1
Note: VOH is defined as the DC output high voltage when the device is loaded with a 1 k resistor to ground.
tOH and tH0
Note: VOL is defined as the DC output low voltage when the device is loaded with a 1 k resistor to VCC.
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MM74C240 * MM74C244
Physical Dimensions inches (millimeters) unless otherwise noted
20-Lead Small Outline Integrated Circuit (SOIC), JEDEC MS-013, 0.300" Wide Package Number M20B
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MM74C240 * MM74C244 Inverting * Non-Inverting Octal Buffer and Line Driver with 3-STATE Outputs
Physical Dimensions inches (millimeters) unless otherwise noted (Continued)
20-Lead Plastic Dual-In-Line Package (PDIP), JEDEC MS-001, 0.300" Wide Package Number N20A
Fairchild does not assume any responsibility for use of any circuitry described, no circuit patent licenses are implied and Fairchild reserves the right at any time without notice to change said circuitry and specifications. LIFE SUPPORT POLICY FAIRCHILD'S PRODUCTS ARE NOT AUTHORIZED FOR USE AS CRITICAL COMPONENTS IN LIFE SUPPORT DEVICES OR SYSTEMS WITHOUT THE EXPRESS WRITTEN APPROVAL OF THE PRESIDENT OF FAIRCHILD SEMICONDUCTOR CORPORATION. As used herein: 1. Life support devices or systems are devices or systems which, (a) are intended for surgical implant into the body, or (b) support or sustain life, and (c) whose failure to perform when properly used in accordance with instructions for use provided in the labeling, can be reasonably expected to result in a significant injury to the user. www.fairchildsemi.com 8 2. A critical component in any component of a life support device or system whose failure to perform can be reasonably expected to cause the failure of the life support device or system, or to affect its safety or effectiveness. www.fairchildsemi.com

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